SDRAM is a generic name for various kinds of dynamic random access memories (DRAM) that are synchronized with the clock speed of a microprocessor. In this manner, an SDRAM increases the number of instructions that the microprocessor may perform in a given time.
Typically, SDRAMs are fabricated as separate integrated circuits from other system components. The SDRAMs, microprocessor, and other components of the system are interconnected via a system bus. An SDRAM controller, which is placed between the system bus and the SDRAM, facilitates communication between the microprocessor and the SDRAM, and controls the functioning of the SDRAM. Many of the SDRAM controllers are application specific integrated circuits (ASICs), each providing specific functionality for a predetermined SDRAM.
The memory in the SDRAM is organized in banks. Typically, the number of memory banks may range from 2 to 16, or more. Corresponding to each of these SDRAM banks, there is a memory request queue in the SDRAM controller. A memory request basically involves a row address strobe (RAS) command and a column address strobe (CAS) command for accessing data in a memory bank. The controller has a request scheduler and a RAS/CAS generator which processes requests for all the memory banks in an orderly and timely manner. To control the operation of an SDRAM, the controller may use standard signals, such as address, row address select (RAS), column address select (CAS), write enable (WE), and data input/output mask (DQM) assertions.
The controller, typically, may handle multiple requests from different requestors, such as multiple processors. The controller may arbitrate among these different requestors and grant service (reading data from or writing data to a memory bank) to each requestor in an orderly manner.
In an SDRAM, when a row address and a column address of the initial data have been specified, subsequent addresses are automatically generated to output data in succession synchronously to a clock. The number of data (burst length) provided in succession may be selected by a number, such as 2, 4, or 8. In a burst mode for data accesses synchronously to the clock, data may be read out at a higher speed, since data are accessible per clock.
Because SDRAM memory cells are capacitive, the charge they contain dissipates with time. As the charge is lost, so is the data in the memory cells. To prevent this from happening, an SDRAM must be refreshed. This is done by periodically restoring the charge on the individual memory cells. In addition, the SDRAM may use a feature called auto pre-charge, which allows the memory chip circuitry to close a page automatically at the end of a burst. Auto pre-charge may be used, because the burst transfers are of a fixed length, and the end time of the transfers is known.
Long lead times are typically required to develop and manufacture a custom device, such as an SDRAM controller. Moreover, by the time the SDRAM controller is commercially available, new features may be introduced into the SDRAM, thereby necessitating another design and development of the SDRAM controller and causing more expense. Furthermore, in a multiple requestor environment, the requirement of each requestor for accessing data may change, thereby necessitating yet another design and development phase and causing even more expense.
A need arises, therefore, for a controller that may be used in an application/project and reused in another application/project, without having to undergo an expensive design and development phase. A need also arises for a controller that may accommodate changing needs of a data requestor, as well as the addition or deletion of a data requestor. This invention addresses such needs.